The field of the invention is display systems and in particular graphics processors for display systems that concurrently implement general purpose and DMA processing operations.
Graphics display systems are often implemented with a host processor building and downloading a display list of instructions to a special purpose graphics processor. The graphics processor processes the display list with special purpose instruction processing capability after a complete display list has been downloaded. The time required for the host processor to build and download the display list is often significant compared to the response time requirements. Hence, excessive delays in system response often occur. Also, the graphics processor is often executing a lower priority task while a higher priority task is awaiting processing. Also, the special purpose nature of the graphics processor causes programming inefficiencies and additional delays in system response. Current graphics processors do have some form of general purpose capability. However, it is typically thought that much of the general purpose capability available with micro processors, such as multi-level nested interrupts and nested subroutines, are not appropriate for graphics processors.
It is the standard in the graphics processing industry to completely construct the display list first. Then the display list is processed. In essence, the tasks are performed sequentially. Accordingly, a concurrent graphics processor implemented with DMA downloading would solve the important graphic system problem of fast response.